1

Synoptic

The design has been highly inspired from the SID monitor of the Stanford Solar Center.

1

Schematic

The schematic has been designed using the CadSoft EAGLE Layout Editor.

The RF pre-amplifier section is built around one non-inverting amplifier (IC3A) with a gain of 200 and an inverting amplifier (IC3B) with a gain adjustable between 0 and 25 by R7.

The signal is then filtered in the tuning section. It feeds a MAX275 (IC4), which is a continuous-time 4th-order active filter. The MAC275 is configured as a bandpass filter; center frequency and gain are adjusted by R101/R201, R102+R100/R202+R200, R103/R203 and R104/R204.
A table listing resistor values for some VLF stations can be downloaded here. It has been defined for a quality factor of each 2nd-order section of 170 and a gain of 4.

MAX275 tuning resistor values

(application/pdf, 11Kb, 02 Jul 2007)

For calculating tuning resistor values for other frequencies, refer to the MAX275 datasheet that contains all formulas.

The next section is the RF post amplifier. The first stage is an inverting amplifier (IC6A) with a gain selectable from 2, 5 or 20. The second stage is a full-wave rectifier and averaging filter peak detector build around IC7A and IC7B. A strength signal is available at the output of this stage.

In the analog output section, IC5A and IC5B filter out and amplify the signal.

Finally, the analog to digital conversion is performed by the 12-bits ADC MAX187 (IC10). Interface to RS232 signal levels is done through a MAX220 (IC8).

Eagle 4.14 Schematics		(application/octet-stream, 326Kb, 21 Jul 2007)
Schematics in PDF format		(application/pdf, 157Kb, 21 Jul 2007)
Components List		(application/pdf, 9Kb, 02 Jul 2007)

To view those files, you need a PDF viewer such as SumatraPDF (Windows):  or Adobe® Reader® (Windows, Mac, Linux): 

1	Board Layout

The layout has been done with the objective to fit in a single layer board. To achieve that, a few straps have been necessary. The receiver fits on a single 100x160mm (3-15⁄16x6-5⁄16″) board.

Eagle 4.14 Board		(application/octet-stream, 49Kb, 21 Jul 2007)
Board in PDF format		(application/pdf, 227Kb, 21 Jul 2007)
Board in PDF format (B&W)		(application/pdf, 226Kb, 21 Jul 2007)
Board in PDF format (B&W and mirrored)		(application/pdf, 226Kb, 21 Jul 2007)
Components Placement in PDF format		(application/pdf, 403Kb, 21 Jul 2007)

Here is a picture of the final board:

0

Tuning

1

Assembly

Last step is to put the PCB in a metallic box with the transformer, fuse and power switch.
See the pictures herebelow for assembly example.

1	RS-232 Interface

Here are some details regarding the data transfer protocol between the MAX187 and the RS-232 interface.

The MAX187 signals are connected to the following RS-232 pins:

• /CS ↔ RTS
• SCLK ↔ DTR
• DSR ↔ DOUT

The RS-232 standard defines the positive voltage levels for logic one and negative voltage level for logic zero.

Protocol is detailed in the following documents:

•  MAX187 Datasheet
•  Maxim application note 827. This note contains a C code example.

The overall sequence is described below:

• Unset RTS (RTS=-5V; /CS='1') to deselect MAX187
• Set DTR (DTR=+5V; SCLK='0')
• Set RTS (RTS=+5V; /CS='0') to select MAX187. This starts the conversion.
• Wait till the conversion is done (DOUT must be '1'; DSR=-5V)
• Clock in 12 bits. MSB are first:
  • Unset DTR (DTR=-5V; SCLK='1')
  • Set DTR (DTR=+5V; SCLK='0')
  • Read a bit (signal DOUT, DSR)
• Add a 13^th falling edge:
  • Unset DTR (DTR=-5V; SCLK='1')
  • Set DTR (DTR=+5V; SCLK='0')
• Unset RTS (RTS=-5V; /CS='1') to deselect MAX187
• Unset DTR (DTR=-5V; SCLK='1')